Altera's Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system performance and interoperability. The Interlaken IP core also provides the necessary scalability for next-generation platforms. The combination of Altera?s Interlaken IP core in the Stratix® V FPGA with Cavium?s Octeon processors provides high throughput and bandwidth when workloads are at their peak.
To help simplify your design decision process and accelerate your time to market, Altera?s Interlaken IP core on the Stratix V FPGA has been validated with Cavium's Octeon multicore processors. This interoperability assures solution connectivity upfront when you develop with Altera and Cavium.
- Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner PLL
- SOPC Builder Ready: No
- Qsys Compliant: Yes