The Digital Blocks DB9000AXI TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a TFT LCD panel. The DB9000AXI contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface that targets higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth requirements.
The DB9000AXI IP Core can be implemented in an ASIC, ASSP, or FPGA device with an embedded microprocessor, an AMBA AXI / AHB Interconnect fabric, and SDRAM Controller for access to frame buffer memory. Typically, the microprocessor is an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is off-chip DDR / DDR2 / DDR3 SDRAM.
Features
- Wide range of programmable LCD Panel resolutions:
- Maximum programmable resolutions of 4096x2048
- Horizontal pixel resolutions from 16 to 4096 pixels in 16 pixel increments.
- Example LCD Panel high resolutions:
- Digital Cinema Systems (DCI) 2048 x 1080 2K image, 4096 x 2160 4K image, & Cinema Scope HD 2560 x 1080
- 4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536, 1920x1200, 1920x1080, 1680x1050, 1600x1200
- 1600x900, 1440x900, 1366x768, 1280x1024, 1280×768, 1080x1920, 1024x768, 1024x600, 1024x576, 960x540, 800x600, 800x480
- Example LCD Panel medium / small resolutions:
- 640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272
- 480x234, 240x400, 240x320, 240x240, 320x200, 320x240
- Programmable 1 Port or 2 Port TFT LCD Panel interfaces
- Interface for 1 Port TFT LCD Panel:
- 18-bit digital (6-bits/color)
- 24-bit digital (8 bits/color) LVDS / CMOS
- Interface for 2 Port LVDS TFT LCD Panel:
- Two 24-bit digital (8 bits/color) LVDS / CMOS ports
- Programmable frame buffer bits-per-pixel (bpp) color depths:
- 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel
- 16, 18, bpp directly drive 18-bit LCD pixel
- 24 bpp directly drive 24-bit LCD pixel
- Color Palette RAM to reduce Frame Buffer memory storage requirements and AXI Bus bandwidth (for lower color applications):
- 256 entry by 16-bit RAM, implemented as 128 entry by 32-bits
- Loaded via the Slave Bus Interface statically by the microprocessor or the Master Bus Interface dynamically with each frame by the DMA controller
- Programmable Output format support:
- RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface
- RGB 8:8:8 on 24-bit digital interface
- Programmable horizontal timing parameters:
- horizontal front porch, back porch, sync width, pixels-per-line
- horizontal sync polarity
- Programmable vertical timing parameters:
- vertical front porch, back porch, sync width, lines-per-panel
- vertical sync polarity
- Programmable pixel clock:
- pixel clock divider from 1 to 128 of Bus Clock
- pixel clock polarity
- Programmable Data Enable timing signal:
- Derived from horizontal and vertical timing parameters
- display enable polarity
- AMBA AXI / AHB Interconnect:
- Selectable 256 / 128 / 64 / 32-bit AXI Master Port for DB9000AXI DMA access of frame buffer memory for driving the display
- Selectable 256 / 128 / 64 / 32-bit AXI (or AHB) Slave Port for control & status interface to microprocessor
- Three memories:
- 32-word x 64 bit input FIFO, decoupling AXI bus & LCD panel clock rates. Integrated with DMA controller.
- 256-word x 16-bit Color Palette RAM
- 16-word output FIFO
- FIFOs parameterizable in depth and width
- Power up and down sequencing support
- 9 sources of internal interrupts with masking control
- Little-endian, big-endian, or Windows CE mode
- AHB Bus - Compliance with AMBA Specification (Rev 2.0)
- AXI Bus - Designed to AMBA AXI Protocol Specification (V1.0)
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states.
Benefits
- The DB9000AXI IP Core contains programmable features comparable to entry-level ASSP LCD controller chips, including a timing and control unit, pixel depth & unpacking, and a color palette to reduce frame buffer space and AXI bus bandwidth. The Core specifically and cost-effectively targets TFT LCD panels with 1 Port or 2 Ports of 18-bit digital (6-bits/color) or 24-bit digital (8-bits/color) interface.
- The DB9000 family of TFT LCD Controllers support the following bus interfaces:
- AMBA 2.0 AHB Master, AHB Slave
- CoreConnect PLB, OPB
- Avalon
- OCP 2.2
- PCI
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
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