PCI Compiler, 64-bit Target

Features

• Contains 32-bit PCI master/target, 32-bit PCI target, 64-bit PCI master/target, 64-bit PCI target MegaCore® functions
• Fully compliant with the timing and functional requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0
• Extensively tested in hardware
• Easy SOPC Builder-ready integration using the general-purpose, full-featured bridge
• Intellectual property (IP) functional simulation models provide cycle-accurate behavioral simulations in industry-standard Verilog HDL and VHDL simulation tools
• Open-source PCI testbench provides flexible PCI bus functional models to verify Altera® PCI MegaCore function-based applications in industry-standard Verilog HDL and VHDL simulation tools
• Reference designs for popular functionality implemented on the local side of the PCI MegaCore functions, including direct memory access (DMA) engines, datapath FIFO architectures, and SDRAM interfaces