The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane Ethernet) standard draft for 100GBASE-CR4 and 100GBASE-KR4 PHY. The encoder and decoder functions are completely independent and packaged as two sub-cores, RS100-E and RS100-D respectively. Decoder corrects up to 7 word errors. A lightweight error-detection-only decoder RS100-DM is also available and can be used for the bit stream alignment where the error correction feature is not necessary.
- The core implements the FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard). 100G Ethernet MAC-friendly interface. Core features include:
- Syndromes Error Detection flag
- Correctable and Non Correctable Error flags
- The core is practically self-contained: requires only an external buffer memory in the decoder.
- Flow-through design; low latency
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- User Documentation
- 100GBASE-CR4 and 100GBASE-KR4 PHY