This AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, with 128-bit key.
Basic core is designed only for encryption and is very small (less than 3,000 gates). Enhanced versions are available that support encryption and decryption for various cipher modes (ECB, CBC, OFB, CFB, CTR), as well as different datapath widths for size/performance tradeoff.
The core includes the key expansion logic.
- Encrypts using the AES Rijndael Block Cipher Algorithm
- Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
- Processes 128-bit data blocks with in 8, 16 or 32-bit data interface
- Employs key size of 128 bits
- Includes the key expansion function
- Simple, fully synchronous, reusable design
- Completely self-contained: does not require external memory
- Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
- Extremely compact design (less than 3K gates for TSMC 0.18 process)
- HDL Source Licenses
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- Simulation script
- Synthesis script
- User Documentation