Make it EASY with Synopsys DesignWare DDR HARD PHY IP

By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars

Posted on Friday Feb. 25, 2011