Configurable PCI Express 2.0, 1.1 Controller IP for ASIC/SoC

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Synopsys Demonstrates SuperSpeed USB 3.0 InteroperabilityThis demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.Gervais Fong Product Marketing Manager, USB PHY IP Posted on Tuesday Feb. 22, 2011 |
Synopsys Channel
Minimize High-Speed PHY Risk for First Silicon Success 2:41
USB 3.0 and Universal Video Class (UVC)2:04
TLM Central2:49
Delivering Great Audio with an Integrated, SoC-Ready Subsystem Solution 19:45
Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution06:05
The Fastest USB 3.0 Performance in the Universe 2:34
Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY03:20
Understanding MIPI06:26
Synopsys Demonstrates Silicon-Proven Implementation of DesignWare Audio IP08:54
Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability03:04 |