MIPI UniPro Verification IP is compliant with MIPI UNIPRO specification and verifies UNIPRO devices. UNIPRO Verification IP is developed by experts who have worked on complex protocols before.
MIPI UniPro VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Features
- Supports 1.4 MIPI UniPro Specification.
- Supports independent communication in forward and reverse direction simultaneously.
- Supports both D-PHY and M-PHY phyiscal layer support
- Supports both PPI and RMMI interface for simulation without PHY
- Supports up to four D-PHY and M-PHY lanes
- Suports both data link layer frames
- Data Frames
- Control Frames
- PHY layer features
- Transmission and reception of encoded PHY symbols, including access to two PHY escape symbols
- Transmission of PHY IDLE symbols when no data is supplied.
- Detection of PHY IDLE symbols.
- Method to re-initialize the forward Link to overcome error situations
- Provision of different power modes and a method to signal them from transmitter to receiver
- PHY adapter layer features
- Transmission and reception of Data Link layer control symbols and data symbols via underlying PHY
- Lane distribution and merging in multi-lane ports
- Provision of MIPI UniPro power management operating modes
- (Re-)Initialization of the PHY TX path
- Data Link layer features
- Frame composition
- Frame decomposition
- Buffering Mechanism
- Supports frame preemption
- Triggering of PHY initialization
- Supports fine grain testing of flow control
- Support for two traffic classes by priority-based arbitration
- Network layer features
- Packet composition and packet decomposition
- Packet format recognition
- Support for traffic Class
- Error handling
- Transport layer features
- Segmentation and Reassembly
- Segment Composition and Segment Decomposition
- Segment format recognition
- Connections
- End-to-End flow-control
- Error handling
- Supports complete DME functionality
- Supports various kind of Tx and Rx errors generation and detection on D-PHY
- SoT error
- Sync error
- Sync length error
- Ecc error
- Supports various kind of TX and RX errors generation and detection on M-PHY
- Disparity errors
- Invalid control chars
- Invalid sync sequence errors
- Timeout conditions injections
- Out of sequence errors
- CRC errros
- Link init errors
- Supports networks of up to 128 devices.
- Transport layer supports multiple bidirectional connections (T_CO_SAP) between endpoint devices.
- Monitor,Detects and notifies the testbench of all protocol and timing errors.
- Supports constraints Randomization.
- Status counters for various events in bus.
- Callbacks in transmitter and receiver for various events.
- MIPI UniPro Verification IP comes with complete test suite to test every feature of MIPI UniPro specification.
- Functional coverage for complete MIPI UniPro features.
Benefits
- Faster testbench development and more complete verification of MIPI UniPro designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
Deliverables
- SmartDV's MIPI UniPro Verification env contains following.
- Complete source code of BFM and monitor.
- Complete regression suite containing all the MIPI UniPro testcases.
- Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.