12bit, 32 GSPS ADC Ultra Low Power
This 12-bit, 32GSPS ADC supports input signals from 0.4-to-16 GHz and features a full-scale range of 0.8V pp differential, excellent dynamic performance and low noise operation.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption. The RF input is internally buffered and sampled and then distributed efficiently to time-interleaved ADC channels.
The ADC includes built in calibration to remove time interleaving artifacts, including offset mismatch, gain mismatch and timing skew.
To maximize SNR, the ADC includes an ultra-low-jitter clock distribution network with aperture jitter of 30fsrms.
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