The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The High Throughout version (AES-X) is more compact can process 128 bits/cycle. The Higher Throughput version (AES-X2) can process 256 bits/cycle.
The AES-XTS core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
- Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
- Implemented according to the IEEE P1619™/D16 standard
- Capable of processing 128 bits/cycle
- Employs user-programmable key size of 128 or 256 bits
- Two architectural versions:
- High throughput version can process 128 bits/cycle
- Higher throughput version can process 256 bits/cycle
- Arbitrary IV length
- Works with the integrated key expansion function
- Simple, fully synchronous, reusable design
- Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
- Complete deliverables include test benches, C model and test vector generator
- The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation.
- The ASIC version includes
- HDL RTL source code
- Sophisticated HDL Testbench (self checking)
- C Model & test vector generator
- Simulation script, vectors & expected results
- Synthesis script
- User documentation
Block Diagram of the Advanced Encryption Standard Core IP Core