The CAN2TSN IP subsystem implements a CAN-to-TSN Ethernet gateway. It enables low-latency, bidirectional communication between up to seven CAN bus ports and one Time-Sensitive Networking Ethernet port. IEEE802.1AS compliant AVB/TSN stack is part of the line of automitive IP cores from CAST, Inc.
The CAN ports can be connected to the same or different CAN networks, and each is independently programmable with the payload type (CAN 2.0 or CANFD) and data rate. The Ethernet port is connected to a 10/100/1000 Mbit network, and supports gPTP/IEEE 802.1AS timing synchronization and traffic shaping according to the IEEE 802.1Qav and IEEE 802.1Qbv standards.
The CAN2TSN timestamps received CAN messages, encapsulates them to UDP frames, and transmits them over Ethernet. In the opposite direction, the CAN2TSN accepts UDP frames encapsulating CAN messages, and extracts and forwards each to one of the CAN ports for transmission.
Each CAN port is associated with a UDP destination port and represents a traffic class for traffic shaping purposes on the Ethernet side. The latency in both direc-tions, CAN to Ethernet and Ethernet to CAN, is extremely low (<30µs), making the gateway suitable for real-time control applications.
To simplify system integration, the CAN2TSN uses standard interfaces and requires minimal software assistance. It interfaces with the SoC via AMBA™ AXI4 buses. It connects to the Ethernet PHY via a standard MII, GMII, or RGMII interface, and to the external CAN transceivers via an industry-standard three-wire (Rx, Tx, STBY) in-terface. The gateway implements DHCP, ARP, ICMP, UDPIP, IEEE 802.1Qav, and IEEE 802.1Qbv with custom hardware; only part of the gPTP stack is implemented in software to allow easy adaptation to future versions of the timing synchronization protocol. The lightweight gPTP software stack runs under FreeRTOS, and can be easily ported to another real-time operating system.
The CAN2TSN is designed with industry best practices, and is available in synthe-sizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, testbench, and comprehensive documentation.