The Synthesizable DDR DRAM PHY from Cadence Design Systems is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Cadence Denali PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
- Achieves up to 1333Mbps PHY including synthesis, layout, and timing closure in 4 hours using a standard EDA toolset
- Process node independent
- Configurable for data width, ECC, and DFI LPI options
- Clear, readable, synthesizable RTL
- Verilog sample testbench with Cadence memory models, encrypted memory controller, and sample tests
- Synthesis and STA Scripts