The Synopsys DesignWare® Multi-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increasing the write cycle endurance specification. The NVM IP is ideal for applications such as passive and semi-passive tags used in radio-frequency identification (RFID) and near-field communication (NFC), as well as other low-power analog and wireless applications. Originally developed in industry standard 180-nm/3.3V processes, the reprogrammable NVM IP enables the MTP functionality required by the Gen2 EPC and ISO15693 RFID standards with best in class power consumption.
Delivered as a hard IP block, the DesignWare MTP ULP NVM IP operates from a single 1.8V supply (including read operation down to 0.85V) and includes all the necessary support and control circuitry, including all high-voltage generation and distribution required for programming.
At the system level this integration will reduce complexity of design and the ultra low-power operation extends battery life, improves RFID tag sensitivity and reduces size of external components such as RF antennas.
Optimized for power consumption and designed in 180-nm process technology, the DesignWare NVM IP meets the needs of ultra-high frequency (UHF) and high frequency (HF) passive RFID tags in the industry’s most cost effective RF processes. Based on a production proven, Synopsys patented bitcell, yield and reliability targets required by high volume applications are achievable.
Zero mask adder, single poly, floating gate, logic-only reprogrammable NVM solution
128-bit to 1K/4K-bit configurations
Minimum of 100,000 write cycle endurance
Minimum 10-year data retention at 85°C
50% area reduction over existing solutions
90% program power reduction over existing solutions
<10µA peak current during program and erase
Read down to 0.85V
Silicon-characterized and qualified to meet industry standards
Front-end views (datasheet, Verilog behavioral model, test bench, .lef)