The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
The system has an internal state machine to control the operation, which can be externally configured via the SPI interface. A typical system application is shown in Figure 1.
This DVB-C QAM demodulator is supplied as a portable and synthesizable Verilog-2001 IP. The system is designed to be used in conjunction with a standard cable tuner. The QAM signal is acquired blindly, and QAM signal constellations from QAM 16 through QAM 256 are supported. The operation of the demodulator is automated by a master finite state machine.
- DVB-C EN 300 429 & ITU-T J.83 Annex A & Annex C compliant QAM demodulator
- Supports IF input
- QAM constellations 16, 32, 64, 128 and 256
- Symbol rates up to 7 MBaud
- Blind acquisition of QAM constellation sizes
- Parallel and Serial MPEG outputs
- 3 external clocks, or 2 external, 1 internally generated
- SPI port (Slave) to external processor
- Synthesizable Verilog-2001
- System Model (Matlab) and documentation
- Verilog Test Benches
- FPGA testing environment
- Set-top boxes
- Cable receivers
- Digital cable ready TV sets
Block Diagram of the DVB-C Demodulator IP Core