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FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
The FPD LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 LVDS Differential Data Pairs and 1 LVDS Differential Clock Pair.
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Block Diagram of the FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
FPD LVDS Display Interface IP
- LVDS FPD Display Interface Transmitter IP (Silicon Proven in GF 65LPe/ /55LPe)
- LVDS FPD Display Interface Transmitter IP (Silicon Proven in GF 28nm)
- LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)
- LVDS Display Interface Transmitter IP (Silicon Proven in STMicro 28FDSOI)
- LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
- FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability