Mn_nH MnHEVC is high performance compact HEVC encoder IP.
HEVC is high efficient bit rate video codec, but use many complex encoding tools. Especially 32x32 transform and RDOQ are most important tools for high efficient bit rate, but too difficult to implement hardwired logic. MnHEVC support almost all encoding tools for high efficient bit rate.
MnHEVC is specialised for competitive SOC system with small area, low power architecture, bus bandwidth reducing technology, optimised specification and what’s more reasonable royalty.
MnHEVC is best SOC IP solution for network camera, car DVR, action and wearable camera.
- HEVC Main profile and up to High tier Level 5
- Max Bit Rate : 100Mbps @ 200Mhz
- Max CU size : 32×32, Min CU size : 4×4
- Max partition depth : 3 (from 32×32 to 8×8, 4×4 All CU Estimation)
- Max TU depth : 1 (Max TU size 32×32, Min TU size 4×4)
- SSE based mode decision
- Intra prediction mode : 0 ~ 35 all estimation
- PU size : 2Nx2N, 2NxN, Nx2N, NxN all estimation
- 2 AMVP, 5 Merge MV all estimation
- All CU motion estimation respectively, configurable wide motion search range
- Quater Pel Motion Estimation
- CABAC VLC, Complex cabac pattern RDOQ
- LCU Dequant for contents adaptive QP control
- Deblock filter and SAO filter
- Transfer data compression technic : bus bandwidth typical 40 % reduction
- Low latency encoding support : 3 ms under
- Decoder : Optional self stream playback support
- RTL design (verilog)
- Testbench on user system memory model (verilog)
- Encoder driver and API C source
- FPGA test program
- PC - FPGA (Encoder - DDR) standalone test program C source
- Bit accurate C-Model for FPGA verification
- Documentation : Datasheet, User Manual