SILABTECH is offering unique High Resolution and High Speed ADC & DAC IPs at advance technology nodes with up to 3.5 Giga Sample Per Second (GSPS) of 8 bit resolution sampled data (7ENOB).
Low Power and Low Area IPs with embedded Low Jitter PLL based clocking system for Industrial, RF (e.g. 60GHz band) and other high speed applications.
The ADC and DAC both support 48 cycle data latency.
These IPs work at 1.1V core voltage supply to reduce the total SOC power consumption.
Support one-shot and continuous conversion modes.
Serial and Parallel digital interfaces to read-out ADC and DAC codes.
The design can scale up to 8bit/28Gsps ADC on 16nm process while keeping similar low power figures.
Custom ADC & DAC designs are available- Contact us for details.
- Analog to Digital Converter (ADC) design is based on interleaved SAR architecture, where each SAR ADC work on 440MHz and 8 ADC’s are interleaved to achieve 3.52GHz data/sampling rate.
- The SAR is based on asynchronous clocking mechanism which helps in optimizing the settling and decision time in each individual ADC.
- The differential design support the settling of common mode internally.
- Input signal voltage - 500mVpp differential.
- The ADC design internally terminates the ADC input with 100 ohms differential resistor with common mode of 900mV.
- The data from ADC are available on each phase of 3.52GHz clock or can be provided in <63:0> format on 440MHz ADC clock.
- SILABTECH 8-bit Differential Current Steering DAC is based on 1.1V supply.
- The design supports 50 ohms Differential Termination with output voltage swing of 500mVpp differential. The output voltage swing is programmable from 400mVpp to 600mV differential.
- SILABTECH DAC supports common mode voltage programmability from 0.8V to 1.1V (supply).
- The differential termination of 50 ohms also is programmable to remove/calibrate the on-chip resistor variation.
- This DAC can take input data at different input rates and re-align the data internally, like 64 bit data at 440MHz or 32 bit at 880MHz.
- Silabtech High Speed and High Resolution ADC and DAC are based on novel design approached and years of analog design experience.
- Silabtech ADC and DAC have signiciantly low power and area comparing to other IPs in the market with similar sampling rate and resolution.
- The SAC ADC basic block of 8bit/440Mhz can be provided as a stand alone IP. Lower Sampling rates can be also offered based on this design.
- Silabtech is offering this IP in other technologies such as 28nm, 16FF and also 40 and 65nm.
- Documents: Functional, DFT, Integration and Test specification
- Simulation Views: RTL Netlist + Sdf
- Timing: .libs
- Physical: Lef, gds, etc
- Test patterns: Scan, TFT & Functional patterns
- High frequency (like 60GHz) OFDM systems transmitter
- Multi Gigabit wireless LAN
- High frequency radio systems
- Software Defined Radio
- Satellite receivers
- High speed link communication
- Ultra-Wideband Radio-Over-Fiber Systems
Block Diagram of the High Speed ADC/DAC 8bit / 3.52Ghz GF 40LP Silicon Proven