ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
PCIe4/3/2/1 PHY & Controller
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
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