MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
SLVS-MI/MIPI-DPHY Transmitter 4-Lane 2500Mbps
The CL12821I4T2JM2NIP2500 converts the input parallel data to the serial data and output it.
The CL12821I4T2JM2NIP2500 is designed to support maximum 2.5Gbps data rate utilizing SLVS-MI or mipi-DPHY_specification_v1-2
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