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Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
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SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemented on FPGA and ASIC technologies.
Features
- SPI-compatible interface
- AMBA APB3 bus
- Master or slave mode
- Full duplex
- Programmable clock rate up to PCLK/2
- Slave speed up to PCLK/8
- Up to 8 slave select lines
- Slave MISO output enable generation for multiple slaves
- Configurable clock polarity and phase
- LSB or MSB mode
- 8, 16, 24, 32 bits data transfer mode
- Maskable interrupts
- Dedicated upstream and downstream DMA interface
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Silicon and FPGA proven
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Block Diagram of the SPI Serial Peripheral Interface Master/Slave
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SPI IP
- AHB Quad SPI Controller with Execute in Place (70115)
- AHB Octal SPI Controller with Execute in Place (70114)
- Flash SPI controller master/slave
- Quad-SPI FLASH Controller AHB
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- SPI Flash Memory Controller