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SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemented on FPGA and ASIC technologies.
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Block Diagram of the SPI Serial Peripheral Interface Master/Slave
SPI IP
- AHB Quad SPI Controller with Execute in Place (70115)
- AHB Octal SPI Controller with Execute in Place (70114)
- Flash SPI controller master/slave
- Quad-SPI FLASH Controller AHB
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- SPI Flash Memory Controller