MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes

Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 4.5Gb/s per lane and 3.5Gs/s per trio respectively for a maximum speed of 24Gb/s. DesignWare C-PHY/DPHY addresses energy requirements by supporting low-power state modes and delivering below 1.3pJ/bit at maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The DesignWare C-PHY/D-PHY IP interoperates with Synopsys’ ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.

• see the entire Synopsys MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes datasheet
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