Ultra low power C-programmable Baseband Signal Processor core

Features

• Ultra low power consumption
• 31 µW/MHz @ 0.8 V (65 nm CMOS)
• 70 µW/MHz @ 1.2 V (65 nm CMOS)
• 40 µW/MHz @ 0.8 V (90 nm CMOS)
• 90 µW/MHz @ 1.2 V (90 nm CMOS)
• 53 µW/MHz @ 0.8 V (130 nm CMOS)
• 120 µW/MHz @ 1.2 V (130 nm CMOS)
• 390 µW/MHz @ 1.8 V in (180 nm CMOS)
• Highly optimizing C-compiler software toolkit
• Minimal core size (65k gates), excluding debug interface (6k gates)
• Small memory footprint
• Performance (Worst Case Commercial Conditions, standard VT)
• 150 MHz @ 1.8 V 180 nm CMOS
• 190 MHz @ 1.2 V 130 nm CMOS
• 245 MHz @ 1.2 V 90 nm CMOS
• 300 MHz @ 1.2 V 65 nm CMOS (>5000 MOPS peak)
• A library of building blocks for complex arithmetic, SIMD acceleration, FFT and modem functions is available.

Benefits

• The CoolFlux BSP is available on FPGA board for testing and analyzing. Or you can evaluate the CoolFlux using the software toolkit.

Block Diagram of the Ultra low power C-programmable Baseband Signal Processor core

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