The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the Forward Error Correction block compliant to 3GPP TS 25.212 V 9.5.0
- WCDMA Release 9 Compliant
- Implements Viterbi decoder to address the convolution encoded bit stream as defined in Section 18.104.22.168 of the specification 3GPP TS 25.212 V 9.5.0 Release 9
- Supports all block sizes i.e., K=40 – 504.
- Constraint length of 9
- Configurable Code rate of 1/2 and 1/3 with rate matching for other code rates supported
- Easy interface definition
- Easy support for rate matching and bit collection
- Customization to AXI or Avalon bus interface supported.
- Bit accurate simulation models available for RTL test vector generation.
- Easily portable across various FPGA families from different vendors
- Customization support available
- Optimized for performance and area
- Licensable in Netlist or Verilog or VHDL source format
- Target technology – Xilinx, Altera, Lattice devices
- Test bench
- C, VHDL, Verilog simulation models available
- Detailed technical documentation
- W CDMA Forward error correction block
Block Diagram of the WCDMA Release 9 compliant Viterbi Decoder IP Core