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130nm FTP Non Volatile Memory for Standard CMOS Logic Process
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AXI 4.0/3.0 UVM/OVM SV Master Verification IP
Test and Verification Solutions offers an AXI 4.0/3.0 UVM/OVM Master VIP as part of its asureVIP™ series of offerings. This is a highly flexible and configurable verification IP, which can be easily integrated into any SOC verification environment. The Master VIP has been interoperability tested with a Slave VIP configuration.
The VIP comes with a Bus Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non compliance with ARM AMBA4 AXI4-Stream Protocol version 1.0.
The VIP has been verified for protocol compliance with asureSign – TVS’ own Requirements Traceability tool.
The VIP comes with a Bus Monitor for performing all protocol checks. The monitor also performs key protocol checks and reports errors for non compliance with ARM AMBA4 AXI4-Stream Protocol version 1.0.
The VIP has been verified for protocol compliance with asureSign – TVS’ own Requirements Traceability tool.
Features
- Supports all protocol burst type, burst length , Transfer Size and response Type
- Supports Unaligned Transfer
- Supports Write Strobe
- Supports Narrow Transfer
- Supports Multiple Outstanding Transaction
- Out-of-Order Transaction completion support
- Supports Transfer Interleaving and ordering process
- Atomic Access support
- Quality of Service Signal
- Region Identifier
- User Signal Support
- INCR Burst length support 1 to 256
Benefits
- Highly Flexible, Independent and Configurable AXI Master VIP
- Proven against Silicon Proven VIP
- Less turnaround time in integrating into SOC Verification environments
Deliverables
- VIP user Guide
- AXI 4.0/3.0 Master UVM/OVM VIP
- Sample Scoreboard
- Sample Virtual Sequencer
Block Diagram of the AXI 4.0/3.0 UVM/OVM SV Master Verification IP
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