DDR4 Memory VIP

Features

• DDR models support JEDEC Low Power Memory Device and DDR4 DRAM (JESD79-4)
• Flexible and unencypted SystemVerilog timing class models all timing parameters
• Dynamic runtime configuration of memory parameters between DDR4/3/2 (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter
• Comprehensive protocol checks for all DDR4 commands and sequences, ODT, write leveling, temp control, data mask and DBI, ZQ calibration, Gear Down, Row hammer ACT threshold, and detailed timing checks including jitter and write DQS checks
• Optional DDR commands supported for DLL off-mode operations, Input clock frequency change, Extended temperature usage
• Back door block read/write access of sparse memory and MRS registers
• Supports active and monitor model modes
• Extensive callbacks for error injection
• Tracker log monitors improves debug including MRS configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers
• Interposer style performance metrics and functional coverage tracks bus utilization, bandwidth, command-command latency including bank and bank group analysis, and MR modes selected to isolate performance bottlenecks and ensure all functional modes have been verified
• Vendors supported: Micron, Samsung, Hynix

Deliverables

• DDR4 BFM
• User Guide

• see the entire DDR4 Memory VIP datasheet
• get in contact with DDR4 Memory VIP Supplier