HBM DFI Verification IP provides an smart way to verify the HBM DFI component of a SOC or a ASIC. The SmartDV's HBM DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
- Compliant with DFI version 4.0 and 5.0 Specifications.
- Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
- Supports all Interface Groups.
- Supports Write Transactions with Data mask
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports Low power control features.
- Supports Error signaling.
- Supports DFI Read/Write Chip Select.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 4.0 and 5.0 Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Faster test bench development and more complete verification of HBM DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the HBM DFI testcases.
- Complete UVM/OVM sequence library for HBM DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.