English
You are here:
- Verification IP Catalog >
- Memory >
- DRAM >
- HBM
HBM Memory Verification IP
HBM-Xactor is a comprehensive memory VIP solution used by HBM memory controller, DFI-PHY and SoC designers to ensure comprehensive verification and protocol and timing compliance. HBM-Xactor implements a complete set of models, protocol checkers, performance analysis, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.
Features
- HBM VIP supports DUT is HMC memory controller and DUT is PHY and supports full set of models including HBM memory module, PHY, and Host memory controller
- Timing class models all timing parameters (callbacks, user modifiable) including quicksim timing modes
- Direct access of Memory banks and MRS registers and wrapper registers
- Inject errors at all layers through callbacks
- Comprehensive protocol and timing checks
- Supports PHY compliance testsuite
- Interposer style performance metrics and functional coverage tracks bus utilization, bandwidth, command-command latency including bank and bank group analysis, and MR modes selected to isolate performance bottlenecks and ensure all functional modes have been verified
- Command tracker log monitors tracks all commands and improves debug
- Dynamic runtime configuration for up to 8 channel/stack, Bank groups, DRAM Density
- Supports IEEE 1500 port and wrapper commands supported including AWORD/DWORD remapping
- Supports Legacy and Pseudo-Channel modes and advanced features for power down and refresh, self-refresh, Auto precharge and Implicit precharge in pseudo channel modeVendors supported: Samsung, Hynix
Deliverables
- HBM BFMs
- Compliance Testsuite
- User Guide
View HBM Memory Verification IP full description to...
- see the entire HBM Memory Verification IP datasheet
- get in contact with HBM Memory Verification IP Supplier