Softnautics JTAG Verification IP is reusable, configurable, pre-verified, and plug-and-play verification component. It provides a comprehensive set of protocols, methodologies, and verification features to achieve rapid verification of designs using JTAG.
It supports Universal Verification Methodologies (UVM) and legacy methodologies through a unique flexible architecture. It is developed in System Verilog. We provide full access to source code for easy integration of JTAG VIP into the test bench.