MIPI Specifications establish standards for hardware and software interfaces between the processors and peripherals typically found in mobile terminal systems.
The MIPI CSI-2 VIP is an interface between a digital imaging module such as a host processor and image sensor peripheral such as a camera. It is available as a CSI-2 Receiver or Transmitter VIP.
eInfochips’ MIPI CSI-2 VIP is based on the layered architecture of object oriented programming that allows coverage driven verification suitable for verifying transmitter and receiver with either of them as DUT.
- The OVM 2.0 Class based MIPI CSI-2 VIP is a readymade, highly configurable, SystemVerilog Verification IP suitable for verification of MIPI CSI-2 Transmitter/ Receiver/ Transmitter with D-PHY/ Receiver with D-PHY/ D-PHY/ Transmitter and Receiver with D-PHY DUTs and for coverage measurement. The VIP can be easily configured and integrated with the verification environment.
- MIPI CSI-2 Supported Features:
- 4 virtual channels
- All synchronization short packets
- RGB, YUV and RAW long packet data types
- Interleaved and normal frames
- Inoperative and operative mode of frame number/line number
- CCI read and write transactions
- Directed, constrained and fully random testing mode
- Configurable transaction generation for each device model
- Fully configurable fields of short and long packets
- Monitors and checkers for protocol violations
- Coverage report generation
- Standard sequences for various types of frames/packets
- User-defined frame formats
- MIPI D-PHY BFM Supported Features
- 1~4 PHY data lanes and 1 clock lane
- Unidirectional data transfer in forward direction
- High-speed data transmission as D-PHY Master
- High-speed data reception as D-PHY Slave
- eInfochips is a MIPI Alliance member.
- Completely verified MIPI Verification Component encrypted code
- Documentation - User's Guide, Release Notes
- Sample test bench
- Sample Test cases
Block Diagram of the MIPI® CSI -2 OVM 2.0 Class based Verification IP