The MIPI CSI-2 Verification IP provides an effective & efficient way to verify the components interfacing with MIPI CSI-2 interface of an ASIC/FPGA or SoC.
The MIPI CSI-2 VIP is fully compliant with Standard MIPI CSI-2 Version 1.1 specifications from MIPI Alliance. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.
- Compliant to MIPI CSI‐2 Specification version 1.2 along with MIPI CPHY
- Specification version 1.1 with PPI interface.
- C‐PHY supports MFEN and SFEN for CSI‐2 TX and RX respectively for Data Lane Module.
- Support for configurable number of lane, low Power Escape.
- Configurable ULPS mode and other CSI2 configuration using CCI
- Supports Data Lane distribution and merging in case of multi‐Lane
- Supports High‐Speed mode and Low Power Escape and Control
- Supports 16:7 Mapper and 7:16 Demapper
- Supports symbol encoding and decoding
- Supports dynamically configurable modes.
- Supports all Short and Long packet formats.
- Supports ECC and CRC generation as well as correction/detection.
- Supports all primary and secondary CSI‐2 data formats.
- Supports Frame/ Line Synchronization.
- Supports both Data Type Interleaving and Virtual Channel
- Interleaving frames.
- Strong Protocol Monitor with real time exhaustive programmable
- checks available for each LLP, LM and PHY layer.
- Supports Dynamic as well as Static Error Injection scenarios at both
- Protocol and PHY layer.
- On the fly protocol checking using protocol check functions, static
- and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Transmitter and
- Graphical analyzer for all Layers to show transactions for easy
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment.
- MIPI CSI-2 TX/RX BFM/Agent
- MIPI CSI-2 Monitor and Score board
- CCI Master/Slave BFM/Agent
- Test Environment & Test Suite :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Compliance Tests
- Integration Guide, User Manual and Release Notes
Block Diagram of the MIPI CSI-2 with C phy Verification IP