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Switching regulator, inductor-based, PWM mode, high efficiency, DELTA standard
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OCP Verification IP
OCP Verification IP provides an smart way to verify the OCP component of a SOC or a ASIC. The SmartDV's OCP Verification IP is fully compliant with standard OCP Specification 2.2 and provides the following features.
OCP VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
OCP VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
Features
- Compliant to OCP Protocol
- Supports OCP Master, OCP Slave, OCP MOnitor, OCP Checker.
- Support all OCP Protocol data and address width
- Support all OCP Protocol transfer types and response
- Support all OCP Protocol burst transfers
- Multiple outstanding transactions
- Assertions and Checks for protocol violations
- Logs and report for bus traffic
- Also includes User-configurable commands
- Call backs and call back variables to provide control over test case execution
- On-the-fly protocol and data checking
Benefits
- Faster testbench development and more complete verification of OCP designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
Deliverables
- Complete SystemVerilog source code of OCP Monitor and BFM.
- Complete regression suite containing all the OCP testcases.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
View OCP Verification IP full description to...
- see the entire OCP Verification IP datasheet
- get in contact with OCP Verification IP Supplier