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PCI Express Verification Component
The PCI Express eVC can be used for verification of a device that supports the PCI Express standard. The eVC is compliant to PCI Express Base Specification revision 1.0, 22nd July 2002. It expedites creation of a more efficient testbench for the Device Under Test (DUT) and can operate with both Verilog and VHDL environments. It can perform with all HDL simulators that are supported by Specman Elite™.
Features
- Supports Point-to-Point & Fabric topologies as PCI Express port
- Support for Transaction Layer Packet Protocols
- Support for Data Link Layer Packet Protocols
- Support for Physical Layer Packet Protocols (Logical Block)
- Selectable stand-alone or simulator verification mode
- Configurable support for scoreboard implementation
- Supports loop-back mode
- Configurable validation rules check for each layer
- Configurable sequence generator for injecting random, directed-random as well erroneous test cases for transactions
Block Diagram of the PCI Express Verification Component Verification IP
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