azPHY 1.0 is a perfect solution to verify high speed interface serdes IPs that support the high speed standards e.g. PCIe, USB and SATA. This VIP consists of modular components viz. azPHY model, azMAC uvc and azPIPE interface analyzer. azPHY is a systemverilog based PIPE 4.3 compliant PHY model. azPIPE is a set of assertions to verify the correctness of the PIPE interface and azMAC is a UVC to mimic the controller behaviour.
- Plug-n-play Phy verification solution
- azPHY is fully compatible to PIPE specification Ver 4.3
- azPHY supports driving real values on the srial line with variable de-emphasis, preshoot and swing.
- azPIPE is an independent set of assertions and can be plugged in at the PIPE interface
- azMAC is capable of generating all PHY related scenarios mimicking a PCI Express/USB or SATA controller.
- Support for error injection on Tx and Rx side
- Transmitter equalization support
- Quick turn around time for high speed serdes verification
- One stop solution for serdes related features and PIPE standard related features for complete PHY verification
- Readily available test suite to run and find bugs.
- Configurable data rates, bus width and number of lanes.
- All combinations of data rate, data width abd PCLK frquency supported.
- PHY Model
- Back-to-Back testbench
- Exhastive test suite
- User Guide
Block Diagram of the PIPE 4.3 compliant PHY Verification IP Verification IP