RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus. The SmartDV's RapidIO Verification IP is compliant with RapidIO Trade Association, RapidIO Interconnect Specification version 1.3 and 2.1. RapidIO VIP is implemented in a layered fashion. Whichis basically divided into a physical layer, transport layer and logical layer. The SmartDV's RapidIO Verification IP has both the incarnations of RapidIO technology :Parallel RapidIO and Serial RapidIO(SRIO).
The RapidIO VIP monitor acts as powerful protocol-checker, fully compliant with RapidIO specification. The RapidIO VIP includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.
RapidIO VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Supports RapidIO specification 1.3,2.0 and 2.1.
- Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
- Supports XTBI like interface for testing after PCS layer.
- Supports XGMII like interface for testing before PCS layer.
- Supports 3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s.
- 66, 50, or 34-bit addressing on the RapidIO interface.
- Supports Parallel Physical 8/16 bits interfaces.
- Supports all types of packets and sizes.
- Supports 8-bit or 16-bit device IDs
- Automatic freeing of resources used by acknowledged packets
- Supports I/O system, message passing and globally shared distributed memory (GSM).
- Supports communication with mailboxes via messages.
- Supports generation and reaction to flow control.
- Supports out of order transaction delivery based on the prioritization.
- Supports critical request flow ordering.
- Very flexible to insert errors in serial lanes.
- Supports Error Management Extensions.
- Provides error injection and error detection with a wide variety of error types. Which includes,
- Under and oversize packet.
- CRC errors
- Invalid code group insertion
- Invalid /K/ characters insertion
- Lane Skew insertion
- Received S bit parity error on packet/control symbol
- Error on control symbol
- Oversized and undersized packets
- unsupported packet types
- Supports cancellation and retrying of packets mechanisms.
- Support all types of timing and protocol violation detection.
- Supports constraints Randomization.
- Status counters to keep track of various events.Which includes
- Corrupted/uncorrupted packets
- uncorrupted/uncorrupted control symbols
- Type of packet
- CRC error
- Total number of errors detected
- Supports callbacks for user to get packets or errors in INITIATOR/TARGET and monitor.
- Rapidio verification IP comes with complete testsuite to test every feature of Rapidio spec and also as per RIO LAB testsuite.
- Functional coverage for each functional condition in env.
- Notifies the testbench of significant events such as transactions, warnings, timing and Protocol violations
- Rich set of configuration parameters to control the functionality
- Faster test bench development and more complete verification of RAPIDIO designs.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete testsuite to test every feature of Rapidio spec and also as per RIO LAB testsuite.
- Examples's showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.