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Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR4 based designs. VC VIP DDR4 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP DDR4 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.
Features
- JESD79-4 JEDEC DDR4 SDRAM device standard
- 3DS support
- MRAM support
- Built-in UDIMM, SODIMM, RDIMM, and LRDIMM
- Write leveling, GearDown mode training, per DRAM addressability, jitter
- Temperature controlled refresh, Data Bus Inversion (DBI) and max power savings mode.
- Bank group, fine granularity refresh and self-refresh abort
- Write CRC, CA parity and multi-purpose registers
- Connectivity test mode
- Address mirroring
- Delay modeling : Fly by Delay, Trace Delays, Pre- and Post-buffer delays
- DFI monitor
Benefits
- SystemVerilog and Verilog testbench
- Native UVM and VMM support runs natively on all major simulators
- Protocol-aware debug
- Built-in verification plan and coverage
- Built-in protocol checks
- HTML based documentation
Block Diagram of the Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
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