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Synopsys Verification IP for LPDDR2
Synopsys® VC Verification IP for the JEDEC LPDDR2 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR2 based designs. VC VIP LPDDR2 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP LPDDR2 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.
Features
- JESD209-2F JEDEC LPDDR2 Standard
- 64Mb to 8 Gb densities and x8, x16 and x32 wide SRAM devices
- Write leveling and ZQ Calibration
- Power Off Sequence, Self Refresh, Deep Power Down, Partial Array Self-Refresh
Benefits
- SystemVerilog and Verilog testbench
- Native UVM and VMM support
- Runs natively on all major simulators
- Protocol-aware debug
- Built-in verification plan and coverage
- Built-in protocol checks
- HTML based documentation
- Source code visibility
Block Diagram of the Synopsys Verification IP for LPDDR2 Verification IP
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