As many of my readers have experienced, getting your first silicon in the lab can be an exciting albeit nervous moment. In this post I am showing 20-nm silicon results – eye diagrams with excellent performance of some of the popular interface IP’s such as USB, PCI Express and MIPI. These all came up working first time on 20-nm in our characterisation labs. My engineering team did not leave anything to chance to ensure right first time results.
Let’s first look at the 20-nm process. The impact of this process on physical IP s had both challenges and benefits. The benefits included higher transition frequency (fT) and more transconductance (gm) of the transistor that enable faster designs with more gain. We also took the opportunity to re-design architectures to improve on power, performance and area at 20-nm. The challenges included new layout requirements that involve supporting double patterning technology (DPT), density requirements for metal and polysilicon, lower transistor output conductance (gd).