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Verilog has a very limited and simple hierarchy. All processes are present in static modules. In some ways, System Verilog extends this concept of hierarchy with the support for dynamic data type of class. In System Verilog processes are also present inside dynamic objects. System Verilog updates to fork-join constructs, make the process more flexible and dynamic.

However, this also increases complexity of using processes in System Verilog. What makes it tricky is process usage in the context of object oriented programming. I know that sounds counter intuitive. Object Oriented Programming is good, right? What I mean is, not all the constructs of System Verilog are compatible with object-oriented interpretation. This limited support of object-oriented programming leads to confusion.

In this article I plan to provide the details of three such sources of confusion I have faced. I start off with a refresher about the updates to the fork-join construct in System Verilog. The refresher is followed by top three sources of confusion with examples.