Industry Expert Blogs

If you’ve ever watched a Formula 1 race, you may have wondered how the cars reach race speeds up to 360km/h (223mph). Part of the magic is of course the very advanced and powerful engines. The design of F1 engines is extremely precise, enabling these sophisticated machines to be compact, lightweight, and highly efficient. However, no less important are all the other elements surrounding the engine that are designed to maximize its efficiency.

In the video above, you can see how every single element of each tiny system in the vehicle is painstakingly designed to optimize airflow, decrease heat and weight, maintain a low center of gravity, generate more horsepower, maximize fuel usage, stabilize the driver and, together with the engine, meet the many other goals needed to be an F1 contender. If you’re interested in the math behind how the F1 engines can efficiently reach 1,000 HP, you can check out this video.

While Weebit isn’t designing race cars, we are very focused on optimizing the performance of our ReRAM. As such, we focus not only on the performance of the ReRAM array, but also use a broad range of smart engineering techniques in the Weebit ReRAM module which surrounds our memory array, to maximize that performance.

At the recent 15th IEEE International Memory Workshop (IMW) 2023, Bastien Giraud, a research engineer from CEA-List, presented, “Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro,” a new paper written by CEA-List, CEA-Leti and Weebit.

The paper shares various design assist techniques used in development of the Weebit ReRAM module – some of the important methods that help us to optimize performance parameters. This includes state-of-art custom programming strategies including Read-Before-Write (RBW), Current Limiter (CL), Write Termination (WT), Write Verify (WV) and Error Correction Code (ECC), driven by a flexible Smart Write Algorithm (SWA). The authors describe how each one of these techniques enhances the intrinsic performance of the ReRAM.

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