Industry Expert Blogs

Verification engineers spend roughly one-third of their time debugging their designs, which is about the same amount of time needed to increase verification coverage to detect these bugs. Clearly this is a huge lift, one that becomes even more burdensome as chips continue to grow larger and more complex. And if you’re working on a multi-die design? Well, all this time and effort to provide assurance that the chip will function as intended goes up exponentially. Therefore, to address growing debug challenges and increase overall productivity for verification flows, we’ve tapped into a combination of innovative and hyper-convergent technologies to create the next-generation Synopsys Verdi debug and verification management platform.

The key challenge is that many debug solutions necessitate a manual process to get to the root of the failures. Automation, of course, eases the burden, and even more so if the automation is enhanced by AI. Indeed, AI is enhancing productivity across the chip development spectrum, including in design, verification, and testing. Better silicon quality of results are also evident as intelligent capabilities are integrated into electronic design automation flows.

A painstaking process with results that can be unpredictable, debug is an ideal candidate for an AI-driven uplift. The next-generation Synopsys Verdi platform is enhanced with an AI-driven debug capability as well as comprehensive verification management functions, making the solution ideal for collaboration amongst geographically distributed project teams. Read on to learn how companies like MediaTek are improving debug productivity by as much as 10x using the newest features in the Verdi platform.

What’s Driving Debug Complexity?

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