Xilinx provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The core is designed to work with the latest Virtex®-6, Virtex-5 and Virtex-4 and Virtex-II Pro and Spartan®-6 platform FPGAs and integrate seamlessly into the Xilinx design flow. The 10GEMAC core is designed to the IEEE 802.3-2005 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN and WAN networks.
The Xilinx 10GEMAC core is another of the SystemIO solutions which provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the 10Gb Ethernet standard. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI LogiCORE using the XGMII Interface.
- Designed to IEEE 802.3-2005 specification
- Configured and monitored through an independent microprocessor-neutral interface
- Optional Statistics counters
- Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled
- Generate customized core using the CORE Generator™ technology
- Cut-through operation with minimum buffering for maximum flexibility in 64-bit client bus interfacing
- Ability to generate core with no physical interface to allow users to connect the PHY-side interface of the core to user logic
- Powerful EtherStats-based statistics gathering
- Programmable Interframe Gap
- Custom preamble preservation mode
- Supports Deficit Idle Control (DIC) for max
- data throughput
- Maintains minimum IFG under all conditions and line rate performance
- Remote Fault/Local Fault signaling at the Reconciliation Sublayer