10Gbit/s Ethernet MAC
XGMAC is an all- RTL design to achieve the lowest possible latency, and is fully compliant with the IEEE802.3 specification. The FIFO application interface can be configured for either Xilinx or Altera.
XGMAC is easily integrated into high end FPGAs such as Virtex 6, 7 series (Xilinx) & Stratix, Arria (Altera).
The smooth integration of the XGMAC into your product is supported by reference designs, concise code documentation, and access to expert engineers.
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Block Diagram of the 10Gbit/s Ethernet MAC IP Core
Ethernet IP
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