The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission. BCH is optimal for applications where errors are non-correlated (non-burst) such as NAND flash.
The Cyclic Design BCH IP encodes data into a 16383-bit codeword (2^14 Galois Field), enabling up to 1800 data bytes per correction block with up to 32 bits of ECC. This enables support for next-generation 3x nm flash devices that require 24+ bit ECC over 1KB blocks. Block size and ECC level can be dynamically changed for each correction operation, allowing flexibility in the design of the application controller.
The control interface is optimized around a 16-bit datapath to enable applications using DDR flash devices (8-bit can be supported with a thin wrapper to handle data multiplexing). The data interfaces are FIFO-oriented and a simple control interface eases integration into the application controller.
- 2-40 bit error correction
- 2-1800 data bytes per block
- Low-latency, synchronous design
- Pipelined correction operation supports 3 concurrent corrections
- 16-bit data path (optional 8-bit wrapper available)
- LFSR supports shifting of 2, 4, or 8 bits per cycle.
- Chien Search supports 4, 8, or 16 corrections per cycle.
- Design verified in >50 billion FPGA correction cycles
- Verilog source and documentation
- Synthesizeable verilog testbench