Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.3ba for 40Gbps and 100Gbps Ethernet. The HSEC implements the Multi-Lane Distribution (MLD) protocol layer, the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is world’s first implementation of the IEEE 802.3ba specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers separate from the MAC. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in Virtex® FPGA families.
- Full 100G and 40G Ethernet line rate operation.
- Optional Frame Check Sequence (FCS) checking, adding and deleting.
- Static and dynamic de-skew functions.
- PCS Lane Marker insertion and deletion.
- PCS Lane framing and de-framing including swapping of each PCS Lane.
- Inter-Packet Gap (IPG) insertion and deletion as required by 802.3ba.