Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property
Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.32012 for 40Gbps and 100Gbps Ethernet. The HSEC implements the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is the world’s first implementation of the IEEE 802.32012 specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers standalone with optional Auto_Negotiation and FEC for backplane applications. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in UltraScale and Virtex® FPGA families.
- Full 100G and 40G Ethernet line rate operation.
- Optional fee based Auto-Negotiation and FEC features for MAC + PCS or standalone PCS IP
- Optional Frame Check Sequence (FCS) checking, adding and deleting.
- Static and dynamic de-skew functions.
- PCS Lane Marker insertion and deletion.
- PCS Lane framing and de-framing including swapping of each PCS Lane.
- Inter-Packet Gap (IPG) insertion and deletion as required by 802.32012.