Synopsys' DesignWare® ARC® EM4 is based on the next-generation ARCv2 Instruction Set Architecture (ISA) and pipeline. At less than 10K gates, the core's small size makes it ideal for embedded and deeply embedded applications such as sensors and actuators, memory cards, SSD controllers, 8- and 16-bit microcontroller replacement and battery-operated products.
The DesignWare ARCv2 architecture is a combined 16-/32-bit ISA that is compatible with the existing ARCv1 architecture used on the ARC 600 and 700 families. The ARCv2 ISA is implemented with a new scalable pipeline that enables the development of advanced RISC microprocessor cores with the optimum balance of performance, power consumption and size for a broad range of applications, giving designers a complete processor solution for their system-on-chip (SoC) designs.
The DesignWare ARC EM4 processor core is designed to deliver unmatched performance efficiency (DMIPS/mm2 and DMIPS/mW). Its high degree of configurability enables design teams to optimize the ARC EM4 for a specific application's performance, power and size requirements.
The ARC EM4 features native AHB, AHB-lite and BVCI interfaces to enable high system throughput. The core is fully supported by a complete suite of development tools, including the acclaimed MetaWare Development Kit that generates highly efficient code, the ARC simulators including xCAM and xISS, and the ARChitect® configuration tool.
- A highly configurable architecture allows SoC designers to include only the processor features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
- User-defined instruction and register extensions deliver 5-100 times performance improvement of critical routines.
- 16-/32-bit Instruction Set Architecture for the smallest code size.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.