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- Supports ciphering of multiple sessions in a time multiplexed fashion (maximum number of sessions is parametrically defined at compile time).
- Direct interface to context (state/key) memory.
- CPU i/f provided through the core to initialize and access context memory, simplifies memory i/f logic.
- 256 cycles required to initialize each session context.
- After context has been initialized, the core sustains a throughput of 8 bits every 4 cycles (e.g. 500 Mbps throughput at 250MHz).
- Simple external interface
- Zero overhead context switching.
- Available in ASIC and FPGA technologies.
- Minimal gate count implementation.
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Multi-threaded stream ciphering algorithm