55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
ASIP-1
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Block Diagram of the ASIP-1 IP Core
Programmable IP
- 512x8 Bits OTP (One-Time Programmable) IP, 12FFC 0.8V/1.8V
- Deep Neural Network Programmable Accelerator
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
- 4Kx8 Bits OTP (One-Time Programmable) IP, 22nm FDX 0.8V/1.8V
- 1x64 Bits OTP (One-Time Programmable) IP, GlobalFoundries 22nm FDX 0.8V/1.8V
- 8Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V/5V BCD GIII