MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Asynchronous FIFO alternate design
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Asynchronous FIFO IP
- Asynchronous FIFO with flags and depth counter
- Configurable UART with FIFO, software and hardware flow control
- UART : Universal Asynchronous Receiver Transmitter Core
- Universal Asynchronous Receiver / Transmitter
- Synchronous Universal Asynchronous Receiver/Transmitter
- I3C Master / Slave Controller w/FIFO (APB Bus)