MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Camellia Accelerator
Designed for fast integration, low gate count, and maximum performance, the IP Camellia Engine provides a reliable and cost-effective Camellia IP solution that is easy to integrate into SoC designs.
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