Performs SEU detection, correction, and classification when used in conjuntion with the Frame ECC hard blocks.
- Automatically detects, corrects, and classifies SEU errors
- Supports error injection so all aspects of a system can be evaluated
- Supports up to 100 MHz clock.
- Functions as "Intelligent Sensor" that connects to the system
- Includes simple UART interface to connect to either a terminal or embedded processor
- Supports VHDL and Verilog
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.